`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/10/27 14:42:03
// Design Name: 
// Module Name: Clock
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Clock(
   input clk,
//    input pause,
 //   input rst,
    output reg clk_1ms,
    output reg clk_10ms,
    output reg clk_100ms,
    output reg clk_1s 
//    output [21:0]count
    );
    
    reg [31:0]q;
    reg [31:0]p;
    reg [31:0]r;
    reg [31:0]s;
    
    always @(posedge clk)
           if(r==50000000)
           begin
           r<=0;
           clk_1s<=!clk_1s;
           end
           else
           r<=r+1;
           
    always @(posedge clk)
    if(s==500000)
    begin
    s<=0;
    clk_10ms<=!clk_10ms;
    end
    else
    s<=s+1;
    
        always @(posedge clk)
    if(q==50000)
    begin
    q<=0;
    clk_1ms<=!clk_1ms;
    end
    else
    q<=q+1;
    
  always @(posedge clk)
      if(p==5000000)
      begin
      p<=0;
      clk_100ms<=!clk_100ms;
      end
      else
      p<=p+1;
      
  
    
  endmodule
